High speed of memory access, and reduced power consumption are features that are demanded from semiconductor devices. In recent years, there has been an effort to reduce power consumption and increase access speed for semiconductor devices. As part of that effort to reduce power consumption, it may be desirable to reduce a standby current of buffers on long signal lines used for signal transmission throughout a semiconductor device. For example, systems may include a transistor having a high threshold voltage (Vth) along with these signal lines in order to disconnect a path of a leak current.
For example, U.S. Pat. No. 6,292,015 describes a buffer implemented as an apparatus including sub-threshold current reduction circuits (SCRC). One example of the SCRC is a circuit having a combination of two channel types of transistors for turning off currents. FIGS. 1A and 1B are schematic diagrams of an example buffer 100 including the SCRC in a semiconductor device. The apparatus includes a first power-supply terminal 101, a first ground terminal 102, a second power-supply terminal (pull-up source) 103 that is driven by a first switching transistor 104 and a second ground terminal (pull-down source) 105 that is driven by a second switching transistor 106. In FIG. 1A, the buffer 100 also includes first to fourth logic gates 107, 108, 109 and 110. The second power-supply terminal 103 and the second ground terminal 105 are coupled to the first to fourth logic gates 107, 108, 109 and 110 in a manner that the first power-supply terminal 101 and the first ground terminal 102 are capable of reducing currents in a standby state and driving logic circuits of the first to fourth logic gates 107, 108, 109 and 110 on a signal path after a reset operation. The first switching transistor 104 and the second switching transistor 106 receive first signals in the beginning of the standby state and are deactivated responsive to the first signals. The first switching transistor 104 and the second switching transistor 106 receive second signals when the buffer 100 is reset from the standby state to an active state, and the logic circuits in the first to fourth logic gates 107, 108, 109 and 110 are activated responsive to the second signals. For example, when sources of n-channel transistors 108b and 110b coupled to the second ground terminal 105 are decoupled from the first ground terminal 102 and change to a floating state, a potential of the floating second ground terminal 105 increases due to subthreshold leakage of currents of the n-channel transistors 108b and 110b. As a result, gate-source voltages (VGS) of the n-channel transistors 108b and 110b become negative and automatically end the subthreshold leakage of currents. Thus, the potential of the floating second ground terminal 105 stops increasing. As shown in FIGS. 1A and 1B, logic levels of input and output nodes of the first to fourth logic gates 107, 108, 109, and 110 during the standby state are maintained after transition to the active state during a reset operation in FIG. 1B. Moreover, by operations of the logic gates, the potentials of the floating second power-supply terminal 103 and second ground terminal 105 during the standby state are also maintained until a reset operation. Therefore, the reset operation from the standby state may be accelerated.
In recent years, deterioration of MOS transistors due to negative bias temperature instability (NBTI) has become a critical issue. In particular, NBTI deterioration may cause an absolute value of a threshold voltage (|Vth|) of a p-channel MOS transistor to increase according to an increase of a temperature of the p-channel MOS transistor while a gate of the p-channel MOS transistor is negatively biased. The same issue may occur to an n-channel MOS transistor having its gate positively biased. However, the deterioration of the p-channel MOS transistor is salient. Because a p-channel MOS transistor that is active for a substantially long time tends to have the NBTI deterioration, the NBTI deterioration can be a concern to a p-channel MOS transistor being active during the standby state, which may last a long time. In FIG. 1A, as p-channel transistors 108a and 110a stay active in the standby state, the p-channel transistors 108a and 110a are more likely to deteriorate, and the threshold voltages (Vth) of the p-channel transistors 108a and 110a are likely to increase. This NBTI deterioration may result in critical access path deterioration due to propagation delays of data and deviation in duty cycles and skews when the data are maintained as in the standby mode. As described above, the SCRC is subject to the NBTI and thus may not be suitable for a current reduction circuit in an access path. For example, semiconductor products may be easily and excessively damaged by test stress voltages in a burn-in process during manufacturing. Thus, a countermeasure circuit for the NBTI deterioration particularly for use in the burn-in process may be desired.
U.S. Pat. No. 6,433,584 discloses a buffer implemented as an apparatus including countermeasure circuits for the NBTI issue described the above. FIGS. 2A, 2B and 2C are schematic diagrams of another example of a buffer 200 in a semiconductor device, including the countermeasure circuits. The buffer 200 includes a first ground terminal 202 and a second ground terminal 203 that is driven by a switching transistor 204. The buffer 200 also includes a first logic gate 205, a second logic gate 206, a third logic gate 207, a fourth logic gate 208 and a fifth logic gate 209, including respective p-channel transistors 205a, 206a, 207a, 208a and 209a coupled to power-supply terminals 201 and respective n-channel transistors 205a, 206a, 207a, 208a and 209a coupled to the second ground terminal 203. During a standby state, the switching transistor 204 is off. The switching transistor 204 receives the second signal when the buffer 200 is reset from the standby state to an active state and activates the first to fifth logic gates 205, 206, 207, 208 and 209 responsive to the second signal. For example, the currents in the buffer 200 may eventually be stabilized due to a subthreshold leakage current limitation of the switching transistor 204, therefore the buffer 200 is still effective in current reduction. As shown in FIG. 2A, a first p-channel transistor 205a is turned off and a first n-channel transistor 205 b is turned on, when an input signal of the first logic gate 205 is constant at a logic high (H) level. Consequently, gates of transistors 206a and 206b are coupled to the second ground terminal 203 in a floating state with a potential higher than a logic low level, since a potential of an input signal of the second logic gate 206 may be determined by a balance between a cut-off current of the first p-channel transistor 205a and a cut-off current of the switching transistor 204. Due to a large threshold voltage (Vth) of the switching transistor 204, a potential of the input node of the second logic gate 206 may be set to an intermediate potential higher than a logic low level (>L). Consequently, a second p-channel transistor 206a is almost activated and the potential of an input node of the third logic gate 207 is set to a logic level of substantially high (˜H). In FIG. 2A, first, third and fifth n-channel transistor 205b, 207b and 209b whose gates are substantially at the logic high level, and second, and fourth p-channel transistor 206a and 208a whose levels at gates are higher than the logic low level may have the gate-source voltage (|VGS|) reduced, and thus stresses due to the NBTI may be reduced. Unlike the buffer 100 of FIGS. 1A and 1B, however, logic levels of input nodes of the third logic gate 207, the fourth logic gate 208 and the fifth logic gate 209 may not be stabilized immediately. This causes an issue in the reset operation. FIG. 2B is the schematic diagram when the buffer 200 is in transition from the standby state to an active state due to the reset operation and the switching transistor 204 is turned on. Because the source of the first n-channel transistor 205b is coupled to the first ground terminal 202, the input node of the second logic gate 206 is set to the logic low (L) level. The remaining input nodes of the third to fifth logic gates 207, 208 and 209 may not be stabilized until output signals from prior logic gates coupled to the remaining input nodes are stabilized. FIG. 2C is the schematic diagram when the buffer 200 is in transition from the standby state to the active state due to the reset operation, showing a second transition upon reflecting the first transition of FIG. 2B. A gate of the second logic gate 206 receives a logic low (L) signal. Because a potential of the gate of the second n-channel transistor 206b is logic low, the second n-channel transistor 206b is turned off. At the same time, a potential of the gate of the second p-channel transistor 206a is logic low, the second p-channel transistor 206a is turned on and provides a signal of a logic high level to the input node of the third logic gate 207. The remaining input nodes of the fourth and fifth logic gates 208 and 209 may not be stabilized until output signals from logic gates coupled to the remaining input nodes are stabilized. From FIGS. 2B and 2C, transitions from the standby state to the active state including transmission of logic levels after resetting takes a significant amount of time, and gates of the transistors keep oscillating until being stabilized. Thus, there may be considerable power consumption due to the oscillation until logic levels of the input nodes are stabilized. The above-mentioned oscillation is so called a metastable state. As known, a period of metastable state may be extended due to deviation in a PN ratio, process voltage temperature (PVT) variation or the degree of symmetry of a circuitry design. Due to the propagation delay during the oscillation of logic levels on a path, the buffer 200 is less suitable for a signal path with large-scale logical stages. Moreover, the buffer 200 may fail to completely turn off the second and fourth p-channel transistors 206a and 208a in the standby state, thus the deterioration due to the NBTI may still remain, even if reduced.
U.S. Pat. No. 7,391,233 discloses another buffer implemented as an apparatus including countermeasure circuits for the NBTI issue. FIGS. 3A, 3B and 3C are schematic diagrams of another example of a buffer 300 in a semiconductor device. This circuit includes a first ground terminal 302 and a second ground terminal (pull-down source) 304 to be driven by a switching transistor 305 and a precharging transistor 303. Sources of n-channel transistors 306b, 307b, 308b, 309b and 310b are coupled to the second ground terminal 304. In transition to a standby state from an active state, the switching transistor 305 is turned off and the precharging transistor 303 is turned on, thus all the potentials in the buffer 300 are set substantially to the logic high level (˜H) and the current consumption may be reduced, if a subthreshold leakage current of the switching transistor 305 is small. During a reset operation in transition to the active state, the switching transistor 305 is turned on and the precharging transistor 303 is turned off, thus first to fifth logic gates 306, 307, 308, 309 and 310 are activated. In FIG. 3A, since potentials of input nodes of the first to fifth logic gates 306, 307, 308, 309 and 310 are set to substantially the same level of the logic high level, the first to fifth p-channel transistors 306a, 307a, 308a, 309a and 310a are substantially turned off and the NBTI deterioration can be remedied. The precharging transistor 303 can be deteriorated due to its being active during the standby state, however this deterioration of the precharging transistor 303 can be tolerated. Because the precharging transistor 303 is not on a signal path, the deterioration of the precharge transistor 303 does not contribute to a propagation delay. Being at the logic high level during the standby state, however, the potentials of the input nodes of the first to fifth logic gates 306, 307, 308, 309 and 310 in the buffer 300 may oscillate in a reset operation transitioning from the standby state to the active state that is represented by asterisk (*), even more easily than the potentials of the input nodes of the circuits in the buffer 200 described earlier with FIGS. 2A-2C. Thus, the buffer 300 may not be suitable for a signal path with large-scale logical stages.